1. Field of the Invention
This invention relates to memory address control devices, and more specifically to a memory address control device which may be used alone or in conjunction with one or more additional control devices, as in a slice processor arrangement, to provide a memory addressing circuit which is highly flexible in its ability to provide addresses to a memory from a plurality of sources or logically derived from a plurality of sources.
2. Description of the Prior Art
Microprogrammable processors conventionally provide an arithmetic and logic unit and an associated register file by which logical or arithmetic operations are performed upon data contained in a primary memory or main storage section of the computer. The primary storage is conventionally accessed through a memory interface unit. Associated with the memory interface unit, the arithmetic and logic unit and the register file is a microprogram control device which provides addresses to a control memory, decodes the instructions contained at the addressed locations of a control memory, and provides control signals to the arithmetic and logic unit, register file, memory interface and control memory.
In the past, the microprogram control device has had limited logical capability in that, in one class of machine, the address of the next microinstruction is provided by the currently executing microinstruction. In another class of machine, a limited capability in the microprogram control device is provided to sequentially access microinstructions by means of a microinstruction program counter which may be incremented upon execution of each successive microinstruction. Such devices usually provide an additional limited capability for executing jump, subroutine and return instructions, the addresses of which may be logically derived from control signals derived from the decoded executing microinstruction.